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MITSUBISHI LSIs MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY BY 4-BIT ) DYNAMIC RAM EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD 4-BIT ) DYNAMIC RAM
DESCRIPTION
This is a family of 1048576-word by 4-bit dynamic RAMs, fabricated with the high performance CMOS process,and is ideal for largecapacity memory systems where high speed, low power dissipation, and low costs are essential. The use of quadruple-layer polysilicon process combined with silicide technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. Multiplexed address inputs permit both a reduction in pins and an increase in system densities. Self or extended refresh current is low enough for battery back-up application.
PIN CONFIGURATION (TOP VIEW)
DQ1 1 DQ2 2 W3 RAS 4 A9 5
26 VSS 25 DQ4 24 DQ3 23 CAS 22 OE
FEATURES
A0 9 18 A8 17 A7 16 A6 15 A5 14 A4
Type name
M5M44405CXX-5,-5S M5M44405CXX-6,-6S M5M44405CXX-7,-7S
RAS CAS access access time time (max.ns) (max.ns)
Address OE Cycle Power access access time dissipatime time tion (max.ns) (max.ns) (min.ns) (typ.mW)
A1 10 A2 11 A3 12 VCC 13
50 60 70
13 15 20
25 30 35
13 15 20
90 110 130
500 400 350
XX=J,TP
Outline 26P0J (300mil SOJ)
Standard 26 pin SOJ, 26 pin TSOP(II) Single 5V10%supply Low stand-by power dissipation CMOS lnput level 5.5mW (Max) * CMOS lnput level 550W (Max) Low operating power dissipation M5M44405Cxx-5,-5S 687.5mW (Max) M5M44405Cxx-6,-6S 550.0mW (Max) M5M44405Cxx-7,-7S 467.5mW (Max) Self refresh capabiility * Self refresh current 120A(max) Extended refresh capability * Extended refresh current 120A(max) Hyper-page mode (1024-bit random access), Read-modify- write, RAS-only refresh CAS before RAS refresh, Hidden refresh, CBR self refresh(-5S,-6S,-7S) capabilities Early-write mode and OE and W to control output buffer impedance All inputs, output TTL compatible and low capacitance 1024 refresh cycles every 16.4ms (A0~A9) 1024refresh cycle every 128ms (A0~A9) * 4-bit parallel test mode capability * : Applicable to self refresh version (M5M44405CJ,TP-5S,-6S,-7S : option) only
DQ1 1 DQ2 2 W3 RAS 4 A9 5
26 VSS 25 DQ4 24 DQ3 23 CAS 22 OE
A0 9 A1 10 A2 11 A3 12 VCC 13
18 A8 17 A7 16 A6 15 A5 14 A4
Outline 26P3Z-E (300mil TSOP)
APPLICATION
Main memory unit for computers, Microcomputer memory, Refresh memory for CRT, Frame Buffer memory for CRT
PIN DESCRIPTION
Pin name A0~A9 DQ1~DQ4 RAS CAS W OE Vcc Vss Function Address Inputs Data Inputs / Outputs Row Address Strobe Input Column Address Strobe Input Write Control Input Output Enable Input Power Supply (+5V) Ground (0V)
1
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
FUNCTION
The M5M44405CJ, TP provide, in addition to normal read, write, and read-modify-write operations,a number of other functions, e.g., hyper page mode, RAS-only refresh, and delayed-write. The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Operation Read Write (Early write) Write (Delayed write) Read-modify-write RAS-only refresh Hidden refresh CAS before RAS refresh Self refresh * Stand-by Inputs RAS ACT ACT ACT ACT ACT ACT ACT ACT NAC CAS ACT ACT ACT ACT NAC ACT ACT ACT DNC W NAC ACT ACT ACT DNC DNC NAC NAC DNC OE ACT DNC NAC ACT DNC ACT DNC DNC DNC
Row address Column address
APD APD APD APD APD DNC DNC DNC DNC
APD APD APD APD DNC DNC DNC DNC DNC
Input/Output Output Input OPN VLD APD OPN APD IVD APD VLD DNC OPN OPN VLD DNC OPN DNC OPN DNC OPN
Refresh Remark YES YES YES YES YES YES YES YES NO
HyperPage mode identical
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : invalid, APD : applied, OPN : open
BLOCK DIAGRAM
COLUMN ADDRESS STROBE INPUT CAS ROW ADDRESS RAS STROBE INPUT WRITE CONTROL INPUT W A0~A9
VCC (5V) CLOCK GENERATOR CIRCUIT VSS (0V)
COLUMN DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
(4) DATA IN BUFFERS DQ1
SENSE REFRESH AMPLIFER & I /O CONTROL
DQ2 DQ3 DQ4 (4) DATA OUT BUFFERS
DATA INPUTS / OUTPUTS
ADDRESS INPUTS
ROW & COLUMN ADDRESS BUFFER
ROW A0~ A9 DECODER
MEMORY CELL (4,194,304 BITS)
OE OUTPUT ENABLE INPUT
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IO Pd Topr Tstg Parameter Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature Conditions With respect to Vss Ratings
-1~7 -1~7 -1~7
Unit V V V mA mW C C
Ta=25C
50 1000 0~70
-65~150
RECOMMENDED OPERATING CONDITIONS (Ta=0~70C, unless otherwise noted) (Note 1)
Symbol VCC VSS VIH VIL Supply voltage Supply voltage High-level input voltage, all inputs DQ1~4 Low-level input voltage others Parameter Limits Min 4.5 0 2.4
-1.0 -2.0
Nom 5 0
Max 5.5 0 6.0 0.8 0.8
Unit V V V V V
Note 1 : All voltage values are with respect to Vss.
ELECTRICAL CHARACTERISTICS (Ta=0~70C, VCC= 5V10%, VSS=0V, unless otherwise noted)
Symbol VOH VOL IOZ II ICC1 (AV) Parameter High-level output voltage Low-level output voltage Off-state output current Input current Test conditions IOH =-5mA IOL = 4.2mA Q floating 0V VOUT 5.5V 0V VIN +6.5V, Other inputs pins=0V
(Note 2)
Min 2.4 0 -10 -10
Limits Typ
ICC2 (AV)
M5M44405C-5,-5S RAS, CAS cycling Average supply current from Vcc, operating M5M44405C-6,-6S tRC=tWC=min. (Note 3,4,5) M5M44405C-7,-7S output open RAS= CAS =VIH, output open Supply current from Vcc , M5M44405C RAS= CAS VCC-0.5V stand-by (Note 6) output open M5M44405C(S) Average supply current M5M44405C-5,-5S from Vcc, refreshing M5M44405C-6,-6S (Note 3,5) M5M44405C-7,-7S M5M44405C-5,-5S Average supply current from Vcc, Hyper-PageM5M44405C-6,-6S Mode (Note 3,4,5) M5M44405C-7,-7S M5M44405C-5,-5S Average supply current from Vcc, CAS before M5M44405C-6,-6S RAS refresh mode (Mote 3) M5M44405C-7,-7S RAS cycling, CAS= VIH tRC=min. output open RAS=VIL, CAS cycling tPC=min. output open CAS before RAS refresh cycling tRC=min. output open
RAS cycling CAS 0.2V or CAS before RAS refresh cycling RAS 0.2V or VCC-0.2V CAS 0.2V or VCC-0.2V W 0.2V(Except for RAS falling edge) or VCC-0.2V OE 0.2V or VCC-0.2V A0~A9 0.2V or VCC-0.2V, DQ=open
ICC3 (AV)
ICC4(AV)
Max Vcc 0.4 10 10 125 100 85 2 1 0.1 125 100 85 125 100 85 105 85 75
Unit V V A A mA
mA
mA
mA
ICC6(AV)
mA
ICC8(AV)
Average supply current from Vcc, Extended-Refresh cycle
(Note 6)
120
A
tRC=125s, tRAS=tRAS min~1s ICC9(AV) Average supply current from Vcc, Self-Refresh cycle (Note 6) M5M44405C(S) RAS=CAS 0.2V output open 120 A
Note 2 : Current flowing into an IC is positive, out is negative. Note 3 : ICC1(AV), ICC3 (AV), ICC4(AV) and ICC6(AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. Note 4 : ICC1(AV) and ICC4(AV) are dependent on output loading. Specified values are obtained with the output open. Note 5 : Column Address can be changed once or less while RAS=VIL and CAS=VIH.
3
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
CAPACITANCE (Ta=0~70C, VCC= 5V10%, VSS=0V, unless otherwise noted)
Symbol CI (A) CI (CLK) CI / O Parameter Input capacitance, address inputs Input capacitance, clock inputs Input/Output capacitance, data ports Test conditions VI=VSS f=1MHz VI=25mVrms Min Limits Typ Max 5 7 7 Unit pF pF pF
SWITCHING CHARACTERISTICS (Ta=0~70C, VCC= 5V10%, VSS=0V, unless otherwise noted, see notes 6,14,15)
Limits Symbol tCAC tRAC tAA tCPA tOEA tOHC tOHR tCLZ tOEZ tWEZ tOFF tREZ Parameter Access time from CAS Access time from RAS Column address access time Access time from CAS precharge Access time from OE Output hold time from CAS Output hold time from RAS Output low impedance time from CAS low Output disable time after OE high Output disable time after WE high Output disable time after CAS high Output disable time after RAS high (Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11) (Note 7) 5 (Note 13) (Note 7) (Note 12) (Note 12) (Note 12,13) (Note 12,13) 5 5 13 13 13 13
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit ns ns ns ns ns ns ns ns ns ns ns ns
Min
Max 13 50 25 28 13
Min
Max 15 60 30 33 15
Min
Max 20 70 35 38 20
5 5 5 15 15 15 15
5 5 5 20 20 20 20
Note 6 : An initial pause of 200s is required after power-up followed by a minimum of eight initialization cycles (RAS only refresh or CAS before RAS refresh cycles). Note the RAS may be cycled during the initial pause . And eight initialization cycles are required after prolonged periods (greater than tREF(max)) of RAS inactivity before proper device operation is achieved. Note 7 : Measured with a load circuit equivalent to 2TTL and 100pF. The reference levels for measuring of output signals are 2.0V(VOH) and 0.8V(VOL). Note 8 : Assumes that tRCD tRCD(max) and tASC tASC(max) and tCP tCP(max). Note 9 : Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. Not 10 : Assumes that tRAD tRAD(max) and tASC tASC(max). No t11 : Assumes that tCP tCP(max) and tASC tASC(max). No t12 : tOEZ(max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT 10A ) and is not reference to VOH(min) or VOL(max). Not 13 : Output is disabled after both RAS and CAS go to high.
4
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Hyper-Page Mode Cycles)
(Ta=0~70C, VCC= 5V10%, VSS=0V, unless otherwise noted, see notes 14,15) Limits Symbol tREF tREF tRP tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tDZO tRDD tCDD tODD tT Refresh cycle time Refresh cycle time * (Note 16) 30 18 5 0 8 13 0 0 8 8 0 0 13 13 13 1 Parameter
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Min
Max 16.4 128 37
Min
Max 16.4 128 45
Min
Max 16.4 128 50
RAS high pulse width Delay time, RAS low to CAS low Delay time, CAS high to RAS low Delay time, RAS high to CAS low CAS high pulse width Column address delay time from RAS low Row address setup time before RAS low Column address setup time before CAS low Row address hold time after RAS low Column address hold time after CAS low Delay time, data to CAS low Delay time, data to OE low Delay time, RAS high to data Delay time, CAS high to data Delay time, OE high to data Transition time Note 14 : The timing requirements are assumed tT=2ns.
(Note 17) (Note 18)
25 10
(Note 19) (Note 19) (Note 20) (Note 20) (Note 20) (Note 21)
50
40 20 5 0 10 15 0 0 10 10 0 0 15 15 15 1
30 13
50
50 20 5 0 13 15 0 0 10 10 0 0 20 20 20 1
35 13
50
Note 15 : VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Note 16 : tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. Note 17 : tRAD(max) is specified as a reference point only. If tRAD tRAD(max) and tASC tASC(max), access time is controlled exclusively by tAA. Note 18 : tASC(max) is specified as a reference point only. If tRCD tRCD(max) and tASC tASC(max), access time is controlled exclusively by tCAC. Note 19 : Either tDZC or tDZO must be satisfied. Note 20 : Either tRDD or tCDD or tODD must be satisfied. Note 21 : tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Limits Symbol tRC tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tCAL tORH tOCH Read cycle time Parameter
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit ns ns ns ns ns ns ns ns ns ns ns ns
RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Read Setup time before CAS low Read hold time after CAS high Read hold time after RAS high Column address to RAS hold time Column address to CAS hold time RAS hold time after OE low CAS hold time after OE low Note 22 : Either tRCH or tRRH must be satisfied for a read cycle.
(Note 22) (Note 22)
Min 90 50 8 40 13 0 0 0 25 13 13 13
Max 10000 10000
Min 110 60 10 48 15 0 0 0 30 18 15 15
Max 10000 10000
Min 130 70 13 55 20 0 0 0 35 23 20 20
Max 10000 10000
5
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
Write Cycle (Early Write and Delayed Write)
Limits Symbol tWC tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL tWP tDS tDH Parameter Write cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Write setup time before CAS low Write hold time after CAS low CAS hold time after W low RAS hold time after W low Write pulse width Data setup time before CAS low or W low Data hold time after CAS low or W low
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit ns ns ns ns ns ns ns ns ns ns ns ns
(Note 24)
Min 90 50 8 40 13 0 8 8 8 8 0 8
Max 10000 10000
Min 110 60 10 48 15 0 10 10 10 10 0 10
Max 10000 10000
Min 130 70 13 55 20 0 13 13 13 13 0 13
Max 10000 10000
Read-Write and Read-Modify-Write Cycles
Limits Symbol tRWC tRAS tCAS tCSH tRSH tRCS tCWD tRWD tAWD tOEH Parameter
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit
(Note 23) Read write/read modify write cycle time ns 10000 10000 10000 ns RAS low pulse width CAS low pulse width 10000 10000 10000 ns ns CAS hold time after RAS low ns RAS hold time after CAS low ns Read setup time before CAS low (Note 24) ns Delay time, CAS low to W low ns (Note 24) Delay time, RAS low to W low (Note 24) ns Delay time, address to W low ns OE hold time after W low Note 23 : tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT. Note 24 : tWCS, tCWD, tRWD and tAWD and, tCPWD are specified as reference points only. If tWCS tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD tCWD(min), tRWD tRWD(min), tAWD tAWD(min) and tCPWD tCPWD(min) (for fast page
mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH) is indeterminate.
Min 109 75 38 75 38 0 28 65 40 13
Max
Min 133 89 44 89 44 0 32 77 47 15
Max
Min 161 107 57 107 57 0 42 92 57 20
Max
6
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
Hyper page Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle, Read Write Mix Cycle, Hi-Z control by OE or W) (Note 25)
Limits Symbol tHPC tHPRWC tDOH tRAS tCP tCPRH tCPWD tCHOL tOEPE tWPE tHCWD tHAWD tHPWD tHCOD tHAOD tHPOD Parameter (Note 26) Hyper page mode read/write cycle time Hyper Page Mode read write/read modify write cycle time Output hold time from CAS low (Note 27) RAS low pulse width for read or write cycle (Note 28) CAS high pulse width RAS hold time after CAS precharge (Note 24) Delay time, CAS precharge to W low Hold time to maintain the data Hi-Z until CAS access OE Pulse Width (Hi-Z control) W Pulse Width (Hi-Z control) Delay time, CAS low to W low after read Delay time, Address to W low after read Delay time, CAS precharge to W low after read Delay time, CAS low to OE high after read Delay time, Address to OE high after read Delay time, CAS precharge to OE high after read
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit ns ns
Min 20 57 5 65 8 28 43 7 7 7 28 40 43 13 25 28
Max
Min 25 66 5 77 10 33 50 7 7 7 32 47 50 15 30 33
Max
Min 30 79 5 92 13 38 60 7 7 7 42 57 60 20 35 38
Max
100000 13
100000 16
100000 16
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 25 : All previously specified timing requirements and switching characteristics are applicable to their respective Hyper page mode cycle. Note 26 : tHPC(min) is specified in the case of read-only and early write-only in Hyper Page Mode. Note 27 : tRAS(min) is specified as two cycles of CAS input are performed. Note 28 : tCP(max) is specified as a reference point only.
CAS before RAS Refresh Cycle
Symbol tCSR tCHR tRSR tRHR tCAS
(Note 29)
Limits Parameter CAS setup time before RAS low CAS hold time after RAS low Read setup time before RAS low Read hold time after RAS low CAS low pulse width
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit ns ns ns ns ns
Min 5 10 10 10 17
Max
Min 5 10 10 10 17
Max
Min 5 15 10 15 22
Max
Note 29 : Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.
Self Refresh Cycle *
Symbol tRASS tRPS tCHS tRSR tRHR
(Note 30)
Limits Parameter CBR self refresh RAS low pulse width CBR self refresh RAS high precharge time CBR self refresh CAS hold time Read setup time before RAS low Read hold time after RAS low
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit ns ns ns ns ns
Min 100 90 - 50 10 10
Max
Min 100 110 - 50 10 10
Max
Min 100 130 - 50 10 15
Max
7
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
Test Mode Specification (Note 31) ELECTRICAL CHARACTERISTICS (Ta=0~70C, VCC= 5V10%, VSS=0V, unless otherwise noted) (Note 2)
Symbol Parameter Test conditions Min Limits Typ Max 145 115 100 145 115 100 145 115 100 120 100 85 Unit
ICC1(AV)
ICC3(AV)
Average supply current M5M44405C-5,-5S RAS, CAS cycling from VCC, M5M44405C-6,-6S tRC=tWC=min. operating (Note 3,4,5) M5M44405C-7,-7S output open Average supply current M5M44405C-5,-5S RAS cycling, CAS=VIH from VCC, M5M44405C-6,-6S tRC=min. refreshing (Note 3,5) M5M44405C-7,-7S output open Average supply current M5M44405C-5,-5S from Vcc, Hyper-PageM5M44405C-6,-6S Mode (Note 3,4,5) M5M44405C-7,-7S Average supply current M5M44405C-5,-5S from VCC, CAS before RAS M5M44405C-6,-6S refresh mode (Note 3) M5M44405C-7,-7S RAS=VIL, CAS cycling tPC=min. output open CAS before RAS refresh cycling tRC=min. output open
mA
mA
ICC4(AV)
mA
ICC6(AV)
mA
Note 31 : All previously specified electrical characteristics, switing characteristics, and timing requirements are applicable to that of test mode.
SWITCHING CHARACTERISTICS (Ta=0~70C, VCC= 5V10%, VSS=0V, unless otherwise noted, see notes 6,14,15)
Limits Symbol tCAC tRAC tAA tCPA tOEA Parameter Access time from CAS Access time from RAS Column address access time Access time from CAS precharge Access time from OE (Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11) (Note 7)
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit ns ns ns ns ns
Min
Max 18 55 30 33 18
Min
Max 20 65 35 38 20
Min
Max 25 75 40 43 25
TIMING REQUIREMENTS (Ta=0~70C, VCC= 5V10%, VSS=0V, unless otherwise noted, see notes 14,15) Read and Refresh Cycles
Limits Symbol tRC tRAS tCAS tCSH tRSH tRAL tCAL tORH tOCH Parameter Read cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Column address to RAS hold time Column address to CAS hold time RAS hold time after OE low CAS hold time after OE low
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit ns
Min 95 55 13 45 18 30 18 18 18
Max 10000 10000
Min 115 65 15 53 20 35 23 20 20
Max 10000 10000
Min 135 75 18 60 25 40 28 25 25
Max 10000 10000 ns ns ns ns ns ns ns ns
Read-Write and Read-Modify-Write Cycles
Limits Symbol tRWC tRAS tCAS tCSH tRSH tCWD tRWD tAWD Parameter Read write/read modify write cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Delay time, CAS low to W low Delay time, RAS low to W low Delay time, address to W low (Note 23)
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit ns ns ns ns ns ns ns ns
(Note 24) (Note 24) (Note 24)
Min 114 80 43 80 43 33 70 45
Max 10000 10000
Min 138 94 49 94 49 37 82 52
Max 10000 10000
Min 166 112 62 112 62 47 97 62
Max 10000 10000
8
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
Hyper page Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle, Read Write Mix Cycle, Hi-Z control by OE or W) (Note 25)
Limits Symbol tHPC tHPRWC tRAS tCPRH tCPWD tHCWD tHAWD tHPWD tHCOD tHAOD tHPOD Parameter (Note 26) Hyper page mode read/write cycle time Hyper Page Mode read write/read modify write cycle time RAS low pulse width for read or write cycle (Note 27) RAS hold time after CAS precharge (Note 24) Delay time, CAS precharge to W low Delay time, CAS low to W low after read Delay time, Address to W low after read Delay time, CAS precharge to W low after read Delay time, CAS low to OE high after read Delay time, Address to OE high after read Delay time, CAS precharge to OE high after read
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit ns ns ns ns ns ns ns ns ns ns ns
Min 25 62 70 33 48 33 45 48 18 30 33
Max
100000
Min 30 71 82 38 55 37 52 55 20 35 38
Max
100000
Min 35 84 97 43 65 47 62 65 25 40 43
Max
100000
Test Mode Set Cycle
Limits Symbol tWSR tWHR Parameter Write setup time before RAS low Write hold time after RAS low
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Unit ns ns
Min 10 10
Max
Min 10 10
Max
Min 10 15
Max
9
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
Timing Diagram Read Cycle
(Note 32)
tRC tRAS RAS VIH- VIL- tCSH tCRP VIH- CAS VIL- tRAD tASR A0~A9 VIH- VIL- tRAH
ROW ADDRESS
tRP
tRCD
tRSH tCAS
tCRP
tRAL tCAL tASC tCAH
COLUMN ADDRESS
tASR
ROW ADDRESS
tRCS VIH- VIL- tDZC DQ1~DQ4 (INPUTS) VIH- VIL- tCAC tAA tCLZ
Hi-Z Hi-Z
tRRH tRCH
W
tCDD
tREZ tOHR
DATA VALID
tWEZ tOFF tOHC
Hi-Z
VOH- DQ1~DQ4 (OUTPUTS) VOL-
tRAC tDZO
tOHO tOEA tOCH tOEZ tODD
VIH- OE VIL- tORH
Note 32
Indicates the don't care input. VIH(min) VIN VIH(max) or VIL(min) VIN VIL(max) Indicates the invalid output.
10
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
Early Write Cycle
tWC tRAS VIH- VIL- tCSH tCRP VIH- CAS VIL- tASR VIH- VIL- tRAH tASC tCAH tASR
ROW ADDRESS
tRP
RAS
tRCD
tRSH tCAS
tCRP
A0~A9
ROW ADDRESS
COLUMN ADDRESS
tWCS W VIH- VIL- tDS DQ1~DQ4 (INPUTS) VIH- VIL-
tWCH
tDH
DATA VALID
VOH- DQ1~DQ4 (OUTPUTS) VOL-
Hi-Z
VIH- OE VIL-
11
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
Delayed Write Cycle
tWC tRAS VIH- VIL- tCSH tCRP VIH- CAS VIL- tASR VIH- VIL- tRAH tASC tCAH tASR
ROW ADDRESS
tRP
RAS
tCRP tRSH tCAS
tRCD
A0~A9
ROW ADDRESS
COLUMN ADDRESS
tRCS W VIH- VIL- tDZC tWCH tDS DQ1~DQ4 (INPUTS) VIH- VIL- tCLZ VOH- DQ1~DQ4 (OUTPUTS) VOL-
Hi-Z Hi-Z
tCWL tRWL tWP
tDH
DATA VALID
Hi-Z
tOHO tDZO VIH- OE VIL- tOEZ tODD
tOEH
12
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
tRWC tRAS VIH- VIL- tCSH tCRP VIH- CAS VIL- tRAD tASR A0~A9 VIH- VIL- tRAH
ROW ADDRESS
tRP
RAS
tRCD
tRSH tCAS
tCRP
tASC
tCAH
COLUMN ADDRESS
tASR
ROW ADDRESS
tRCS W VIH- VIL-
tAWD tCWD tRWD
tCWL tRWL tWP
tDZC DQ1~DQ4 (INPUTS) VIH- VIL-
Hi-Z
tDS
tDH
DATA VALID
tCAC tAA tCLZ
Hi-Z DATA VALID Hi-Z
VOH- DQ1~DQ4 (OUTPUTS) VOL-
tRAC tDZO tOEA
tODD tOHO tOEZ
tOEH
VIH- OE VIL-
13
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
Hyper Page Mode Read Cycle
tRAS VIH- VIL- tCSH tCRP VIH- CAS VIL- tRAD tASR A0~A9 VIH- VIL- tRAH
ROW ADDRESS
tRP
RAS
tHPC tCAS tCP tCAS tCP
tRCD
tRSH tCAS
tCPRH tASC tCAH
COLUMN-1
tASC
tCAH
tASC
tCAH
tASR
ROW ADDRESS
COLUMN-2
COLUMN-3
tRCS tCAL W VIH- VIL- tDZC tCAL
tRAL tCAL
tRRH tRCH
tRDD tCDD DQ1~DQ4 (INPUTS) VIH- VIL- tCAC tAA tCLZ VOH- DQ1~DQ4 (OUTPUTS) VOL-
Hi-Z DATA VALID-1 DATA VALID-2 Hi-Z
tWEZ
tCAC tAA tDOH
tCAC tAA tDOH
tREZ tOHR tOFF tOHC
DATA VALID-3
tRAC tDZO VIH- OE VIL-
tCPA tOEA tOCH
tCPA
tOHO tOEZ
tODD
14
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
Hyper Page Mode Early Write Cycle
tRAS VIH- VIL- tCSH tCRP VIH- CAS VIL- tRAH
ROW ADDRESS
tRP
RAS
tRCD
tCAS
tCP
tHPC tCAS
tRSH tCP tCAS tCRP
tASR A0~A9 VIH- VIL-
tASC
tCAH
tASC
tCAL tCAH
COLUMN-2
tASC
tCAL tCAH
COLUMN-3
tASR
ROW ADDRESS
COLUMN-1
tWCS VIH- VIL- tDS DQ1~DQ4 (INPUTS) VIH- VIL-
tWCH
tWCS
tWCH
tWCS
tWCH
W
tDH
tDS
tDH
tDS
tDH
DATA VALID-1
DATA VALID-2
DATA VALID-3
VOH- DQ1~DQ4 (OUTPUTS) VOL-
Hi-Z
VIH- OE VIL-
15
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
Hyper Page Mode Read-Write, Read-Modify-Write Cycle
tRAS VIH- VIL- tCSH tCRP VIH- CAS VIL- tASR A0~A9 VIH- VIL- tRAD tRAH tASC tCAH
COLUMN-1
tRP
RAS
tHPRWC tCAS tCP tCAS
tRWL
tRCD
tCRP
tASC
tCAH
tCWL
tASR
ROW ADDRESS
ROW ADDRESS
COLUMN-2
tAWD tRCS W VIH- VIL- tRWD tDZC DQ1~DQ4 (INPUTS) VIH- VIL-
Hi-Z
tCWL tWP tRCS
tAWD tCWD tWP
tCWD
tCPWD tDS tDH
DATA VALID-1
tDZC
Hi-Z
tDS
tDH
DATA VALID-2
tCAC tAA tCLZ tAA
tCAC tCLZ
DATA VALID -1
VOH- DQ1~DQ4 (OUTPUTS) VOL-
Hi-Z
Hi-Z
tRAC tDZO tOEA
DATA VALID -2
Hi-Z
tODD tOHO tOEZ
tCPA tDZO tOEA
tODD tOHO tOEZ
tOEH
VIH- OE VIL-
16
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
Hyper Page Mode Mix Cycle (1)
tRAS tRWL RAS VIH- VIL- tCSH tCRP VIH- CAS VIL- tRAD tASR A0~A9 VIH- VIL- tRAH tASC tCAH tASC tCAH tASC tCAH tRCD tCAS tCP tHPC tCAS tCP tHPRWC tCAS tCWL
tRP
tCRP
tASR
ROW ADDRESS
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
tRCS tCAL W VIH- VIL- tDZC
tWCS
tWCH tCAL
tCPWD tAWD tCWD
tWP
tDH tDS
tDZC tDS
tDH
DQ1~DQ4 (INPUTS)
VIH- VIL- tAA tCLZ tCAC
DATA VALID-2
DATA VALID-3
tAA tWEZ
DATA VALID -1
tCAC tCLZ
DATA VALID -3
VOH- DQ1~DQ4 (OUTPUTS) VOL-
Hi-Z
tRAC tDZO
tOEA tOCH
tOHO tOEZ tDZO
tCPA tOEA
tOHO tOEZ tOEH
VIH- OE VIL- tODD tODD
17
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
Hyper Page Mode Mix Cycle (2)
RAS
VIH- VIL-
VIH- CAS VIL- tCP tASC A0~A9 VIH- VIL- tCAL VIH- VIL- tHCWD tHAWD tHPWD DQ1~DQ4 (INPUTS) VIH- VIL- tAA tCPA VOH- DQ1~DQ4 (OUTPUTS) VOL- tHCOD tHAOD tHPOD VIH- OE VIL-
Hi-Z
tCAS tCAH
COLUMN-1
tCAS tASC tCAH
COLUMN-2
tASC
tCAH
COLUMN-3
tRCH tWCS
tCAL tWCH
W
tDH tDS
DATA VALID-2
tDZC
Hi-Z
tCAC tWEZ
DATA VALID-1 Hi-Z
tCAC tAA tCPA tCLZ
DATA VALID-3
tOHO tOEZ tODD
tDZC
tOEA
18
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
Hyper Page Mode Read Cycle ( Hi-Z control by OE )
tRAS VIH- VIL- tCSH tCRP VIH- CAS VIL- tRAD tASR A0~A9 VIH- VIL- tRAH
ROW ADDRESS
tRP
RAS
tRCD
tCAS
tCP
tHPC tCAS
tRSH tCP tCAS tCRP
tCPRH tASC tCAH
COLUMN-1
tASC
tCAH
tASC
tCAH
tASR
ROW ADDRESS
COLUMN-2
COLUMN-3
tRCS VIH- VIL-
tRAL
tRRH tRCH
W
tWEZ tDZC DQ1~DQ4 (INPUTS) VIH- VIL- tCAC tAA tCLZ VOH- DQ1~DQ4 (OUTPUTS) VOL-
Hi-Z DATA VALID-1 HI-Z
tRDD tCDD
tCAC tAA tDOH
DATA VALID-1 DATA VALID-2
tCAC tAA tCLZ
Hi-Z
tREZ tOHR tOFF tOHC
DATA VALID-3
tRAC tDZO VIH- OE VIL- tOEA
tOEZ tOHO tOCH tOEA
tCPA tOHO
tCPA tCHOL tOEZ
tOHO tOEZ
tOEPE
tOEPE
tODD
19
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
Hyper Page Mode Read Cycle ( Hi-Z control by W )
tRAS VIH- VIL- tCSH tCRP VIH- CAS VIL- tRAD tASR A0~A9 VIH- VIL- tRAH
ROW ADDRESS
tRP
RAS
tHPC tCAS tCP tCAS tCP
tRSH tCAS tCRP
tRCD
tCPRH tASC tCAH
COLUMN-1
tASC
tCAH
tASC
tCAH
COLUMN-3
tASR
ROW ADDRESS
COLUMN-2
tRCS VIH- VIL- tDZC DQ1~DQ4 (INPUTS) VIH- VIL- tCAC tAA tCLZ VOH- DQ1~DQ4 (OUTPUTS) VOL-
Hi-Z DATA VALID-1
tRAL tRCH tRCS
tRRH tRCH
W
tWPE
Hi-Z
tRDD tCDD
tWEZ
tCAC tAA tWEZ tDOH
DATA VALID-2
tCAC tAA tCLZ
Hi-Z
tREZ tOHR tOFF tOHC
DATA VALID-3
tRAC tDZO
tOEA tOCH
tCPA
tCPA
tOHO tOEZ
VIH- OE VIL- tODD
20
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
RAS-only Refresh Cycle
tRC tRAS RAS VIH- VIL- tCRP VIH- CAS VIL- tASR A0~A9 VIH- VIL- tRAH tASR
ROW ADDRESS ROW ADDRESS
tRP
tRPC
tCRP
W
VIH- VIL-
DQ1~DQ4 (INPUTS)
VIH- VIL-
VOH- DQ1~DQ4 (OUTPUTS) VOL-
Hi-Z
VIH- OE VIL-
21
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
CAS before RAS Refresh Cycle, Extended Refresh Cycle *
tRC tRP RAS VIH- VIL- tRPC tCSR VIH- CAS VIL- tCPN tASR A0~A9 VIH- VIL- tRCH W VIH- VIL- tRRH tRSR tRHR tRSR tRHR
ROW ADDRESS COLUMN ADDRESS
tRC tRAS tRP
tRAS
tCHR
tRPC
tCSR
tCHR
tRPC
tCRP
tRCS
DQ1~DQ4 (INPUTS)
VIH- VIL- tREZ tOHR tOFF tOHC
VOH- DQ1~DQ4 (OUTPUTS) VOL- tOHO tOEZ VIH- OE VIL-
Hi-Z
22
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
Hidden Refresh Cycle (Read) (Note 33)
tRC tRAS RAS VIH- VIL- tRCD tRSH tCHR tRP tRAS
tRC tRP
tCRP VIH- CAS VIL-
tASR A0~A9 VIH- VIL-
tRAD tRAH tASC
ROW ADDRESS
tASR tCAH
COLUMN ADDRESS ROW ADDRESS
tRCS tRAL tRCH W VIH- VIL- tDZC DQ1~DQ4 (INPUTS) VIH- VIL- tCAC tAA tCLZ VOH- DQ1~DQ4 (OUTPUTS) VOL-
Hi-Z DATA VALID Hi-Z
tRRH
tCDD tRDD
tOFF tOHC
tREZ tOHR
Hi-Z
tRAC tDZO VIH- OE VIL-
tOEA tORH
tOHO tOEZ tODD
Note 33 : Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above.
23
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
Self Refresh Cycle *(Note 30)
tRP VIH- VIL- tRPC tCSR VIH- CAS VIL- tCPN
tRASS
tRPS
RAS
tRPC tCHS tCRP
tASR A0~A9 VIH- VIL- tRRH tRCH W VIH- VIL- tRDD tCDD DQ1~DQ4 (INPUTS) VIH- VIL-
Hi-Z ROW ADDRESS COLUMN ADDRESS
tRSR
tRHR
tRCS
tREZ tOHR tOFF tOHC
Hi-Z
VOH- DQ1~DQ4 (OUTPUTS) VOL- tOHO tOEZ VIH- OE VIL- tODD
24
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
Test Mode Set Cycle (Note 34)
tRC tRP VIH- VIL- tRPC VIH- CAS VIL- tCPN VIH- VIL- tWSR tRCH W VIH- VIL- tWHR tASR
ROW ADDRESS COLUMN ADDRESS
tRAS
tRP
RAS
tCSR
tCHR
tRPC
tCRP
A0~A9
tRCS
DQ1~DQ4 (INPUTS)
VIH- VIL- tOFF
VOH- DQ1~DQ4 (OUTPUTS) VOL- tOEZ VIH- OE VIL-
Hi-Z
Note 34 : The cycle is also avaiilable for initialization cycle, but in this case device enters test mode. The test mode function is initiated with a W and CAS before RAS cycle(WCBR cycle) as specified above timing diagram. The test mode function is terminated by either a CAS before RAS(CBR) refresh or a RAS only refresh cycle. During the test mode, the device is internally organized as 4-bits wide (256-kilobytes deep) for each DQ (input/output) port. No addressing of A0,A1(column only) is required. During a write cycle, data on the each DQ (input) pin is written in parallel into all 4-bits for each DQ port and can be written independently for each DQ port. During a read cycle, the each DQ (output) pin indicates independently a HIGH state if all 4-bits are equal, and a LOW state if any bits differ. During the test mode operation, a WCBR cycle is used to perform refresh.
25
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
Note 30 : Self refresh sequence Two refreshing methods should be used properly depending on the low pulse width(tRASS) of RAS signal during self refresh period. 1. Distributed refresh during Read/Write operation (A) Timing Diagram
Read /Write Cycle Self Refresh Cycle Read /Write Cycle
tNSD
tRASS100s
tSND
RAS
last refresh cycle first refresh cycle
Table 2
Read/Write Cycle CBR distributed refresh RAS only distributed refresh Read/Write Self Refresh tNSD125s tNSD16s Self Refresh Read/Write tSND125s tSND16s
(B) Definition of distributed refresh tREF tREF/1024 tREF/1024
RAS
refresh cycle read/write cycles refresh cycle refresh cycle read/write cycles
Definition of CBR distributed refresh (Including extended refresh) The CBR distributed refresh performs more than 1024 constant period (125s max.) CBR cycles within 128ms. Definition of RAS only distributed refresh All combinations of nine row address signals (A0~A9) are selected during 1024 constant period (16s max.) RAS only refresh cycles within 16.4ms. Note: Hidden refresh may be used instead of CBR refresh. RAS/CAS refresh may be used instead of RAS only refresh. 1.1 CBR distributed refresh Switching from read/write operation to self refresh operation. The time interval from the falling edge of RAS signal in the last CBR refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within tNSD (shown in table 2). Switching from self refresh operation to read/write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period should be set within tSND(shown in table 2) 1.2 RAS only distributed refresh Switching from read/write operation to self refresh operation. The time interval tNSD from the falling edge of RAS signal in the last RAS only refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within 16s. Switching from self refresh operation to read/write operation. The time interval tSND from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period should be set within 16s.
26
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
2. Burst refresh during Read/Write operation (A) Timing diagram
Read /Write Self Refresh Read /Write
tNSB
tRASS100s
tSNB
RAS
first refresh cycles refresh cycles 1024 cycles refresh cycles 1024 cycles last refresh Cycles
Table 3
Read/Write Cycle CBR burst refresh RAS only burst refresh Read/Write Self Refresh tNSB16.4ms Self Refresh Read/Write tSNB16.4ms
tNSB+tSNB16.4ms
(B) Definition of burst refresh
16.4ms
RAS
refresh cycles 1024cycles read/write cycles
Definition of CBR burst refresh The CBR burst refresh performs more than 1024 continuous CBR cycles within 16.4ms. Definition of RAS only burst refresh All combination of nine row address signals (A0~A9) are selected during 1024 continuous RAS only refresh cycles within 16.4ms. 2.1 CBR burst refresh Switching from read/write operation to self refresh operation. The time interval ns from the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within 16.4ms. Switching from self refresh operation to read/write operation. The time interval snob from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the last CBR refresh cycle during read/write operatio n period should be set within 16.4ms. 2.2 RAS only burst refresh Switching from read/write operation to self refresh operation. The time interval from the falling edge of RAS signal in the first RAS only refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within tNSB (Shown in table 3). Switching from self refresh operation to read/write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the last RAS only refresh cycle during read/write operation period should be set within tSNB (shown in table 3).
27
M5M44405CJ,TP-5,-5S:Under development

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